CMOS is known as Complementary Metal-Oxide Semiconductor. Some times it is also referred as complementary-symmetry metal–oxide–semiconductor because both N-type and P-type MOSFETs are used in CMOS for designing various types of logic. Nowadays CMOS is being used in the designing of integrated circuits and it has become an integral part of all types of memories. CMOS is not only used in digital circuits, but it is used in analog circuits also. Small power dissipation and high noise immunity are major advantages of the CMOS over other semiconductor devices. Power dissipation does not take place in the static condition.
A small amount Power got dissipated when switching take place in the circuit between on and off states. This is the reason behind the use of CMOS technology in the VLSI circuit design. CMOS is used to design various types of logics such as NOT, AND, OR, NAND, NOR, XOR and XNOR. But Inverter (NOT gate) is treated as basic gate of CMOS technology. This paper will give a detailed description of the static and dynamic CMOS NOR logic. (Impressum, 2007)
Construction of NOR logic using CMOS technology is not very difficult task. First we will see the working of normal NOR gate. Following is the symbol and the truth table of the NOR gate.
A
B
Out
0 (Low)
0 (Low)
1 (High)
0 (Low)
1 (High)
0 (Low)
1 (High)
0 (Low)
0 (Low)
1 (High)
1 (High)
0 (Low)
Figure1: Symbol of NOR gate (referred from CMOS NOR, 2009)
Truth Table
The 2-input NOR gate has been shown in the figure1. Truth tale says that output of this NOR gate would be 1 (high level) when both inputs (A & B) are 0’s (low level) and it would be 0 (low level) for all other combinations of inputs. Now be will talk about the NOR gate using CMOS technology. For 2 input CMOS NOR gate circuit total four MOSFETs are being used: two P channel or P type and two N channel or N type. P channel MOSFETs (M3 and M4) are connected in series between VDD and the output Q. on the other hand N channel MOSFETs (M1 and M2) are connected in parallel between GND and the output Q. capacitor CL is working as a bypass capacitor to enhance the noise margin of the circuit. (Impressum, 2007)
Figure2: Static NOR gate (Sophiep, 1997 “CMOS Dynamic Logic”)
It is the static NOR gate using CMOS technology. In this logic circuit both P-channel and N-channel can separately perform the logic. There may two cases:
1. P-channel replaced by a resistor- output would be
2. N-channel replaced by a resistor- output would be
These two logics are same according to DeMorgan’s Theorem. (Sophiep, 1997)
Now we will talk about the operation of this circuit. There is a concept on which this circuit works. We will see this concept in the following table.
MOSFET
Input at Gate terminal of MOSFET
State (Saturation/Cutoff)
P-channel
1 (High)
Cutoff (open circuit)
P-channel
0 (Low)
Saturation (Short circuit)
N-channel
1 (High)
Saturation(Short circuit)
N-channel
0 (Low)
Cutoff(open circuit)
There may be four combinations of inputs (A & B). On the basis of above table we can detect the output Q.
1. A=0, B=0:
M1 and M2 would be in cutoff region means will act as open circuit. M3 and M4 would be in Saturation region means will act as a short circuit. Means VCC will be connected to the output Q. Hence high voltage level will be detected in the output Q. (Q = 1)
2. A=0, B=1:
M1 and M3 would be in cutoff region means will act as open circuit. M2 and M4 would be in Saturation region means will act as a short circuit. Means VCC will not be connected to the output Q. Out will get connected to the ground (level 0). Hence low voltage level will be detected in the output Q. (Q = 0)
3. A=1, B=0:
M2 and M4 would be in cutoff region means will act as open circuit. M1 and M3 would be in Saturation region means will act as a short circuit. Means VCC will not be connected to the output Q. Out will get connected to the ground (level 0). Hence low voltage level will be detected in the output Q. (Q = 0)
4. A=1, B=1:
M3 and M4 would be in cutoff region means will act as open circuit. M1 and M2 would be in Saturation region means will act as a short circuit. Means VCC will not be connected to the output Q. Out will get connected to the ground (level 0). Hence low voltage level will be detected in the output Q. (Q = 0) (Impressum, 2007)
Now we will talk about the dynamic NOR gate using CMOS technology.
Figure3: Dynamic NOR gate (diagram from: Sophiep, 1997 “CMOS Dynamic Logic”)
Figure4: Graph (diagram from: Sophiep, 1997 “CMOS Dynamic Logic”)
In the above circuit clock signal is used to charge load capacitor CL. There are two conditions:
When the transition takes place from high to low (low voltage) p-channel MOSFET MP would be in saturation stage and capacitor CL will charge through it. It is called Precharge region. At this time n-channel MOSFET ME remains in cutoff stage.
When the transition takes place from low to high (high voltage) n-channel MOSFET ME would be in saturation stage and capacitor CL will charge through it. It is called Evaluate region. At this time p-channel MOSFET MP remains in cutoff stage.
In case of Dynamic NOR gate fan-in becomes large as compare to Static NOR gate. Because of the smaller load capacitances speed of operation also becomes fast. But in dynamic NOR gate clock is essential, which could make the circuit costly and complicated. (Sophiep, 1997)
References
CMOS NOR. (2009). The MathWorks, Inc. Retrieved May 14, 2010 from http://www.mathworks.com/access/helpdesk/help/toolbox/physmod/elec/ref/cmosnor.html
Impressum. (2007). CMOS Gate Demonstration. Retrieved May 14, 2010 from http://tams-www.informatik.uni-hamburg.de/applets/cmos/
Sophiep. (1997). CMOS Dynamic Logic. EE 105 Spring 1997 Lecture 13. Retrieved May 14, 2010 from http://www.prenhall.com/howe3/microelectronics/pdf_folder/lectures/tth/lecture13.fm5.pdf
